1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, to a buffer control circuit of a semiconductor memory device and control method thereof.
2. Discussion of Related Art
In general, a semiconductor memory device includes a data input buffer that receives data from an external device and outputs the externally input data to an internal core circuit including a memory cell array, during a write operation. When the data input buffer is enabled to perform the operation of receiving the external input data, current consumption of the semiconductor memory device rises abruptly. This is because the data input buffer receives the external input data through an external transmission line having a relatively high resistance value.
To reduce current consumption by the data input buffer, it is very important to control the data input buffer to be disabled during the remaining periods except for the period in which the data input buffer must operate. To this end, the semiconductor memory device includes a buffer control circuit for enabling or disabling the data input buffer by generating a control signal.
The construction and operation of the buffer control circuit in the related art will be described in short below with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of a buffer control circuit and data I/O circuits of a semiconductor memory device in the related art.
Data input buffers INB1 to INBJ and data output buffers OUTB1 to OUTBJ of data I/O circuits DATC1 to DATCJ (J is an integer) are connected to I/O pads P1 to PJ, respectively. For example, the data input buffer INB1 and the data output buffer OUTB1 can be connected to the I/O pad P1. The data input buffers INB1 to INBJ are enabled or disabled in response to a buffer control signal ENDINDSB1.
Preferably, when the buffer control signal ENDINDSB1 is disabled, the data input buffers INB1 to INBJ is enabled. When the data input buffers INB1 to INBJ are enabled, they receive external input data WDAT1 to WDATJ, respectively, through the I/O pads P1 to PJ and output internal input data INDAT1 to INDATJ, respectively. The data output buffers OUTB1 to OUTBJ receive the internal output data OUTDAT1 to OUTDATJ, respectively, and output external output data RDAT1 to RDATJ, respectively, to the I/O pads P1 to PJ.
Meanwhile, a buffer control circuit 10 generates the buffer control signal ENDINDSB1 in response to write latency signals WL1 to WL3 and internal control signals CKEBCOM, RASIDLE, DOFFB1, and WTSTDB. In more detail, the buffer control circuit 10 disables the buffer control signal ENDINDSB1 when the internal control signal RASIDLE is disabled and enables the buffer control signal ENDINDSB1 when the internal control signal DOFFB1 or the internal control signal RASIDLE is enabled.
During the read operation of the semiconductor memory device including the buffer control circuit 10, the internal control signal DOFFB1 is enabled while the data output buffers OUTB1 to OUTBJ output the external output data RDAT1 to RDATJ to the I/O pads P1 to PJ, respectively. As a result, the buffer control circuit 10 enables the buffer control signal ENDINDSB1 in response to the control signal DOFFB1 during the period in which the control signal RASIDLE is disabled (i.e., during the active period of the semiconductor memory device). However, in the event that the buffer control circuit 10 generates the buffer control signal ENDINDSB1 based on the control signal DOFFB1, a circuit designer may encounter lots of difficulties in designing the buffer control circuit 10.
In more detail, the buffer control circuit 10 is disposed close to the data input buffer in order to rapidly execute the control operation of the data input buffer. However, a control signal generator (not shown) that generates the control signal DOFFB1 is disposed far away from the data input buffer because it has to receive a variety of control signals of a control circuit block (not shown). As semiconductor chips are miniaturized due to the developments of semiconductor manufacturing technology, however, a designing work for routing a signal line that transfers the control signal DOFFB1 from the control signal generator to the buffer control circuit 10 becomes more difficult.
In the case where the buffer control circuit 10 generates the buffer control signal ENDINDSB1 based on the control signal DOFFB1, a problem arises because the buffer control circuit 10 operates even during a period in which the data input buffers INB1 to INBJ need not to be driven actually. This problem may become more profound when the semiconductor memory device including the buffer control circuit 10 is applied to semiconductor devices in which a plurality of semiconductor memory devices (i.e., memory ranks) are disposed on one chip in the same manner as the memory module.
The operation of the buffer control circuit 10 when the semiconductor memory device including the buffer control circuit 10 is disposed in a memory module will be described below with reference to FIG. 2. It is assumed that the memory module includes first to Uth (U is an integer) semiconductor memory devices (not shown), each of which has the buffer control circuit 10. It is also assumed that after an active command ACT is inputted to the first to Uth semiconductor memory devices at the same time and read commands READ1 to READU are sequentially inputted to the first to Uth semiconductor memory devices, a precharge command PRECH is inputted to the first to Uth semiconductor memory devices at the same time.
In FIG. 2, chip selection signals CSB1 to CSBU are signals for selecting the first to Uth semiconductor memory devices, respectively, and internal control signals DOFFB1 to DOFFBU are generated from the first to Uth semiconductor memory devices, respectively. Furthermore, the buffer control signal ENDINDSB1 enables or disables the data input buffers INB1 to INBJ of the first semiconductor memory device.
If the active command ACT is inputted to the first to Uth semiconductor memory devices at the same time, the first to Uth semiconductor memory devices are respectively activated. Thereafter, if the read commands READ1 to READU are sequentially inputted to the first to Uth semiconductor memory devices, respectively, the first to Uth semiconductor memory devices sequentially operate the read operation. At this time, the internal control signals DOFFB1 to DOFFBU are respectively enabled only when corresponding ones of the first to Uth semiconductor memory devices output the external output data RDAT1 to RDATJ to the outside. It is to be understood that only timing diagrams of the external output data RDAT1 of each of the first to Uth semiconductor memory devices is shown in FIG. 2 for simplification.
The internal control signal DOFFB1 is enabled while the first semiconductor memory device outputs the external output data RDAT1 to the outside. Accordingly, the buffer control circuit 10 of the first semiconductor memory device enables the buffer control signal ENDINDSB1 during a period T1 in which the internal control signal DOFFB1 is enabled and disables the buffer control signal ENDINDSB1 again after the period T1. As a result, the data input buffers INB1 to INBJ of the first semiconductor memory device are disabled during the period T1 and are enabled again after the period T1.
It is not necessary for the data input buffers INB1 to INBJ of the first semiconductor memory device to operate during the period T2 in which each of the second to Uth semiconductor memory devices performs the read operation. As a result, there is a problem in that the data input buffers INB1 to INBJ of the first semiconductor memory device consume power unnecessarily during the period T2.
There is also a problem in which the data input buffers INB1 to INBJ of each of the second to Uth semiconductor memory devices consume power unnecessarily during periods other than the read operation period of each of the second to Uth semiconductor memory devices. This problem may become more profound when the number of semiconductor memory devices included in a memory module is increased.